In this master project you will design and measure a time-to-digital converter focusing on high time resolution. By exploiting the properties of jitter in the time-domain sampler combined with signal averaging, the delay can be measured with a resolution exceeding the unit delay elements used by the sampler.
The system in mind includes a time-to-digital sampler, jitter noise generator and calibration system. This includes tunability of the jitter generator for different jitter probability distributions. True noise generators are challenging to implement while pesudo-nosie solutions are feasible. A major challenge of this project is analysis of noise properties with respect to implementable tunability of CMOS noise generators.