The topic of this master project proposal is to study how we may benefit from having several representations of the same module at the same time and toggle between these. In this project we will start from an amplifier intended to be implemented in an integrated CMOS technology. Subtasks of this project is to develop, analyse and compare these models regarding accuracy, simulation speed, implementation complexity etc. Another subtask is to study how toggling between different representations can be used to develop and verify large integrated circuits more efficiently.
The high integration rate of modern (and future) integrated circuits allows huge complex circuits containing several different types of modules. Such systems on chip (SoC) may contain digital processors and memory, one or more RF interfaces, analog sensor read in, analog actuator control, power measurement, power control and power regulators. The circuit may have different clock and supply voltage domains. Development and verification of these large systems is very challenging. We would like to have very precise analog models showing simulation results very close to the real electrical behaviour. However, the time required for the traditional very accurate and precise analog simulations increases exponentially with complexity and is unacceptable when systems start to grow. Another alternative is to have “signal-flow”, event-based models (Real Number Modelling) and using simulation algorithms behaving more like digital simulators. Such models grow linearly with complexity and are thus much more manageable for larger systems.
In this master project the intention is to develop multiple representations of an analog module exemplified by an operational amplifier. Below follows possible representations of the amplifier. During simulation each module will be represented by the symbol (0) and one of 1 – 5.
1. Symbol drawing with pin names, directions etc. This symbol interface will be common for all the following representations.
2. Simple analog representation with only the most essentials [Example: Vo = A * (Vip – Vin)]. This model may be written in VerilogA, VerilogAMS, SystemVerilog or a schematic with ideal components/sources.
3. An analog representation with the characteristics and limitations given by the design specifications i.e. dc-gain, gain-bandwidth, input and output range, offset, phase margin etc. This model may be written in VerilogA or VerilogAMS.
4. Transistor schematic fulfilling the specifications.
5. Extracted transistor schematic. This requires that a layout has been made and the parasitic from wiring is included in the schematic. This representation may be skipped if the student is not familiar with layout design.
6. Signal-flow event-driven real number model (RNM) written in SystemVerilog. This will be a model that scale much better and is suited as being part of a larger system. This model allows “digital mixed-mode simulation”. This is a new method and a significant part of the project will be to get experience with how RNM can be utilised.
It is also useful to get an impression whether the sequence of the steps above is an efficient strategy for developing new analog modules.
Figure: Each column (example: red frame) contains several different representations of the same module (here: amplifier). The beige boxes require an analog simulator while for the light blue it is sufficient with a signal-flow event-driven simulator. Possible testbench setups may be a) precise analog simulation of one amplifer (i.e. representation 3 or 4 from one column (example: green frame) within a limited testbench environment, b) top level simulation confirming connectivity and functionality of the entire circuit where alle amplifiers (analog modules) are represented by model 5 (example: pink frames), c) a mixed simulation where some analog modules are represented with schematic models while other are represented with Real Number models (example: orange frames). This alternative allows the possibility for both getting an impression of accurate precision at the same time as higher-level connectivity and functionality is confirmed.
The master projects proposal is most suited for a student with both CMOS and programming experience and interest. The student will get experience with Cadence schematic design, VerilogA language coding and SystemVerilog real number language coding. If time allows and the student is interested, it may also include Cadence layout design with extraction. An additional representation in VerilogAMS is also possible.