High-Speed Sorter for Database Acceleration

For example, in a first phase, sorted subsequences may be generated and merged to longer sorted sequences in one or more succeeding phases. As a sorting phase can only start after the preceding one has finished, it is advantageous to implement dedicated sorters for each phase that use as much resources as possible for executing a sort step as quick as possible. Then, runtime reconfiguration will be used to swap the hardware for each sorting step.
For this master thesis, a flexible architecture for accelerating sorting tasks on FPGAs has to be developed. This architecture will be demonstrated on a prototype board.