Module Placement on FPGAs: Offline FPGATris

 

The novel ReCoBus communication architecture allows to place reconfigurable modules in a relatively fine two-dimensional grid on FPGAs (Field Programmable Gate Arrays). This provides a significant utilization improvement for the undelaying host FPGA as compared to previous approaches. However, this implies that the corresponding modules are efficiently packed on the device.

The goal of this master thesis is to develop a module placer that automatically packs a set of given modules (specified by their geometry) on a definable grid. The placer should be able to deal with real world FPGA devices.

 

Existing devices consist of different types of tiles (e.g., logic or memory tiles) that are provided by an FPGA. For a feasible placement, the modules must fit perfectly into these tiles. Furthermore, the placer should be able to deal with design alternatives for the particular modules (e.g., different module shapes, similar to Tetris bricks). This packaging problem is very suitable for constrained programming.


 

Theory (20%), Concepts (50%), Implementation (30%)

Prerequisites: INF1400, INF 2270, INF3430/4430
Apportionment:  
Supervisors: Dirk Koch, Jim Tørresen


 

 

Tags: Hardware Linking for FPGAs
Published Mar. 4, 2010 5:38 PM - Last modified Jan. 18, 2013 11:12 AM