Simulating Runtime Reconfigurable Systems

FPGAs (Field Programmable Gate Arrays) are devices that can be customized with various circuits after manufacturing the chip. Some FPGAs allow for changing fractions of the circuitry loaded to the device while keeping the rest of the system running. This process is called partial runtime reconfiguration. Among manifold further advantages, this technique allows to implement systems on smaller - and therefore cheaper and less power hungry - chips. However, designing runtime reconfigurable systems is difficult, becau-se of a lack in adequate verification techniques.

Throughout this thesis, a simulation framework has to be designed that is in particular capable of simulating effects originating from partially reconfiguring a system on an FPGA. The simulation will be verified with original test data from an FPGA.