Efficient Reconfigurable On-Chip Buses for FPGAs
Abstract
This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration. The buses permit direct connections of master and slave modules to the bus in combination with a flexible fine-grained module placement and with minimized latency and area overheads. A test system will demonstrate a transfer rate of 800 MB/s while providing an extreme high placement flexibility.
Bibtex
@INPROCEEDINGS{fccm08koch, AUTHOR = {{Koch}, {Dirk} and {Haubelt}, {Christian} and {Teich}, {J{\"u}rgen}}}, ADDRESS = {Palo Alto, CA, USA}, BOOKTITLE = {16th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008)}, MONTH = apr, PAGES = {287--290}, PUBLISHER = {IEEE Computer Society}, TITLE = {{Efficient Reconfigurable On-Chip Buses for FPGAs}}, YEAR = {2008}, DATE = {April 14--15}, ISSN_ISBN = {978-0-7695-3307-0} }