Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems

Fine-grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Abstract

The architecture of Xilinx FPGAs, has changed remarkable with respect to their ability to implement runtime reconfigurable systems throughout the last generations. This paper will discuss these changes and reveal an on-FPGA communication architecture that is especially tailored to Xilinx Virtex-5 FPGAs. With this architecture, modules can be integrated in a two-dimensional grid with more than a hundred of individual tiles while allowing a throughput of several GB/s to reconfigurable modules.

Bibtex

@INPROCEEDINGS{fccm10koch,
        AUTHOR             = {{Koch}, {Dirk} and {Beckhoff}, {Christian} and {Jim}, {Torresen}},
        BOOKTITLE          = {18th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010)},
        PUBLISHER          = {IEEE Computer Society},
        TITLE              = {{Fine-grained Partial Runtime Reconfiguration on Virtex-5 FPGAs}},
        year               = 2010,
        month              = may,
        location           = {Charlotte, North Carolina, USA},
        pages              = {69--72}
}