Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation

Efficient Hardware Checkpointing — Concepts, Overhead Analysis, and Implementation

Abstract

Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is an effective methodology to cope with faults. In this paper, we systematically extend the concept of checkpointing known from software systems to hardware tasks running on reconfigurable devices. We will classify different mechanisms for hardware checkpointing and present formulas for estimating the hardware overhead. Moreover, we will reveal a tool that takes over the burden of modifying hardware modules for checkpointing.
Post-synthesis results of applying our methodology to different hardware accelerators will be presented and the results will be compared with the theoretical estimations.

Bibtex

@INPROCEEDINGS{fpga07koch,
        AUTHOR             = {{Koch}, {Dirk} and {Haubelt}, {Christian} and {Teich}, {J\"urgen}},
        ADDRESS            = {{Monterey, California, USA}},
        BOOKTITLE          = {{Proceedings of the 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2007)}},
        PUBLISHER          = {ACM},
        MONTH              = feb,
        PAGES              = {188--196},
        TITLE              = {{Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation}},
        YEAR               = {2007}
}