A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
Abstract
This paper proposes an FPGA-based System-on-Chip (SoC) architecture with support for dynamic runtime reconfiguration. The SoC is divided into two parts, the static embedded CPU sub-system and the dynamically reconfigurable part. An additional bus system connects the embedded CPU subsystem with modules within the dynamic area, offering a flexible way to communicate among all SoC components. This makes it possible to implement a reconfigurable design with support for free module placement. An enhanced memory access method is included for high-speed access to an external memory. The dynamic part includes a streaming technology which implements a direct connection between reconfigurable modules. The paper describes the architecture and shows the advantages in a smart camera case study.
Bibtex
@INPROCEEDINGS{fpl10oetken,
author = {{Oetken}, {Andreas} and {Wildermann}, {Stefan} and {Teich}, {J{\"u}rgen} and {Koch}, {Dirk}},
ADDRESS = {Milan, Italy},
booktitle = {Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)},
MONTH = aug,
PAGES = {234--239},
TITLE = {{A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs}},
year = {2010}
}