Zero Logic Overhead Integration of Partially Reconfigurable Modules
Abstract
Swapping just small fractions of the configuration of an FPGA can be very beneficial in many applications. This is in particular useful for reconfiguring
the instruction set of embedded soft core processors.
In this paper, we will sketch that present design techniques include a material overhead for integrating reconfigurable parts into the rest of the system.
This overhead can cost more logic resources than the actual module implementations. For removing this overhead, we propose a novel technique to
constrain the communication resources between the static system and the partial regions. We will demonstrate for a reconfigurable soft core processor
that instructions can be integrated into the system without causing any additional logic overhead for the communication. In addition, we reveal how such
systems can be easily implemented with our tool ReCoBus-Builder.
Bibtex
@INPROCEEDINGS{fccm10koch,
AUTHOR = {{Koch}, {Dirk} and {Beckhoff}, {Christian} and {Torresen}, {Jim}},
BOOKTITLE = {23rd Symposium on Integrated Circuits and Systems Design (SBCCI)},
PUBLISHER = {ACM},
TITLE = {{Zero Logic Overhead Integration of Partially Reconfigurable Modules}},
year = 2010,
month = sep,
location = {Sao Paulo, Brasil},
pages = {103--108}
}