Disputation: Ali Dadashi

Doctoral candidate Ali Dadashi at the Department of Informatics, Faculty of Mathematics and Natural Sciences, is defending the thesis Ultra-Low-Voltage and Energy-Efficient Circuit
Techniques for iOTs
for the degree of Philosophiae Doctor.

Picture of the candidate

Photo: Private

The PhD defence will be partially digital, in Kristen Nygaards sal (5370), Ole-Johan Dahls hus and streamed directly using Zoom. The host of the session will moderate the technicalities while the chair of the defence will moderate the disputation.

Ex auditorio questions: the chair of the defence will invite the attending audience at Kristen Nygaards sal to ask ex auditorio questions. 

Trial lecture

"Energy-efficient data converters for IoT applications – requirements, architectures and future trends".

Tuesday 11 October 2022, 10:15 am, in Kristen Nygaards sal (5370), Ole-Johan Dahls hus / Zoom

 

Main research findings

  • The main aim of this research is to study and develop new Ultra-Low Voltage and energy-efficient circuit techniques for low power iOT applications. In the digital domain, NP-domino logic technique is studied for relatively high-speed applications while using a power supply as low as 300 mV and below. Semi-Floating Gate technique is used to increase the speed of the conventional domino logic circuits for both single-rail and dual-rail NP-domino configurations. A chip prototype that includes SFG ULV inverter logic gates was also fabricated and successfully measured. The intent was to study the practical challenges of the logic. In the analog domain, energy-efficient circuit techniques are studied for the iOT s. For the LCD displays in iOT devices, a high-speed and energy-efficient buffer amplifier is proposed. Finally, an energy-efficient, successive approximation register analog to digital converter is designed, fabricated and measured during this research, which is suitable for ultra-low-power iOTs. Several techniques have been used to reduce the power consumption. The proposed data converter is powered up by a simple energy harvester in the lab. Utilizing lower supply voltages, minimizing the static currents, designing circuits with different threshold voltages, sleep mode designing, and minimizing leakage currents were the techniques that employed.

Adjudication committee:

 

 

  • Professor Valeriu Beiu, Department of Mathematics and Computer Science, University of Arad, Romania
  • Professor Bengt Oelmann, Department of Electronics Design (EKS), Mid Sweden University, Sweden
  • Professor Dag Wisland, University of Oslo, Department of informatics Norway

 

Supervisors

  • Professor Yngvar Berg,  Department of Informatics, UiO
  • Associate Professor Omid Mirmotahari, Department of Informatics, UiO

 

Chair of defence: 

Associate Professor Ellen Munthe-Kaas

Candidate contact information: https://www.linkedin.com/in/ali-dadashi-028a792b/

Contact information at Department: Mozhdeh Sheibani Harat

Published Sep. 27, 2022 3:58 PM - Last modified Oct. 10, 2022 2:51 PM