Introduction
Traditionally, computer CPUs operate synchronously: a clock syncronizes all processing steps. An adder, for instance, is given two inputs that it has to process during one clock cycle. Just to be sure, the adder is usually designed such that there is a good safety margin included and its result is usually stable well before the clock cycle is finished. And that clock cycle is unfortunately determined by the slowest basic element in the CPU. The extra safety margin wastes a lot of time, but it is necessary, since these elements do sometime work more slowly, dependent on the circuit temperature.
But what if the basic CPU building blocks were designed in a radically different way? What if they could actually signal, when they are finished? A clock would simply not be needed. In a chain of basic operations one instance would simply tell the next when its output is valid and ready to be collected. These circuits are called asynchronous, since they are self-timed and only synchronize to exchange data. There have been CPUs built that way. If you cool them or if you increase the supply voltage, they get faster.
The Project
The aim of this project is to build a simple example of an asynchronous processing circuit, for instance an adder. There are different methods on how to construct asynchronous circuits that the student will have to look into and then come up with a prefered solution. There is still a lot of room for innovation.
Required Skills
ASIC design and chip testing and/or FPGAs. A flair for algorithms. Some experience with parallel processing might come in handy.
Program
Informatikk