EDA tool development for radiation-tolerant logic
The intention of this project is to develop a simple set of tools that incorporate into a flow that will allow rough estimation of the relative single-event transients (SET) cross-sections of combinational logic outputs. Such a tool can be used to highlight critical nodes where SEUs are more likely to occur, and where the designer or optimization tool should try to improve the circuit first.
Initially the flow can use a simple model to approximate the standard cell’s SET generation cross-section and filtering properties. When a baseline flow is complete, the SET/SEU model can be improved and results can be compared for newer generations. An automated (script-based) flow is desirable.
Main goal:
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Create SET analysis tool for gate-level verilog netlists
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Can use Verilog-Perl or similar framework for input netlist parsing
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Find compound SEU cross-section for specific nodes such as DFF inputs.
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Side goals:
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Utilize the SET analysis tool to characterize the tolerance for logic blocks during digital simulation.
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Modeling and SPICE simulation of SET pulse generation and filtering properties for combinational logic cells using custom scripts
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Can be very simple in first iteration: Generation cross-section proportional to AD/AS properties of transistors. Can be made more complex later: Use hspice to find Qcrit for all nodes, for all input conditions.
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