The aim of this project is to develop and improve designs for sequential standard cells in a 180nm process. Important characteristics include power, SEU tolerance, area, and speed. Several designs should be optimized and compared. Design techniques may involve radiation tolerance such as redundancy, temporal redundancy (SET-filtering), DICE.
It is desirable to create a test chip which allows measurements of radiation tolerance, comparing the structures, as well as standard designs. A layout technique to inhibit latch-up should be used. A test structure to perform latch-up characterization should be present on the test chip, the layout for this can be given. A lab measurement setup to characterize the flip-flops should be created, and the chip functionality should be tested. It is possible that the chip could be subjected to a beam to characterize SEE tolerance.