CMOS High speed image sensors exploit parallel structures for read-out, analog to digital conversion (ADC) and even basic preprocessing of the image. Already today there exist sensors that employ column-parallel ADC, or subregion-parallel ADC. The newest image sensors use 3D integration of silicon wavers (i.e. multiple chips on top of each other with 'trans-silicon vias' (TSVs) as contact points between the layers. In such a 3D imager, typically there is a chip with only photo-pixels and some switching logic, and the CMOS layer on top of that holds the ADC and possibly some other processing circuits. A shortcoming of TSVs is that they are relatively big, bigger than a state of the art CMOS imager pixel. Thus, there cannot be one vertical connection per pixel, but multiple pixels (e.g. a column or a subregion of the image) need to (time-)share a single TSV and thus a single ADC and processing unit.
Emerging 3D integration technologies (called sequential- or monolithic 3D integration) try to reduce the vertical connections' size to well below the pixel size and to enable one or even several vertical connections. The Nanoelectroncs group has the fortune to be involved in a European project that is pioneering sequential 3D integration. Also these technologies promise to add much more than merely two or three CMOS layers on top of each-other. This will enable to have a vertical processing column on top of each pixel and thus truly pixel-parallel ADC, processing, and conveyance to memory for extremely high speed imaging in considerable excess of what is possible today.
The technology is still very much experimental and this vision of a high resolution, multi-layer pixel parallel CMOS image sensor is not yet possible. However, a low resolution pixel parallel CMOS image sensor can already be made in a normal single layer CMOS technology. While this is not in itself interesting for the consumer market today, it will be a huge advantage to have experience with ADC designs that shall later be suited for such 3D implementation. Thus we shall attempt to fullfill the appropriate requirements, i.e. foremost a small foot print/transistor count while still delivering sufficient noise performance/signal quality to satisfy the demands of imager consumer products.