3D sequential integration is the topic of an EU project we are involved in together with partner CEA/LETI in France. It promisses to allow 3D CMOS designs where transistors are no longer restricted to just a 2D plane, but can be stacked on top of each-other. In contrast to 'parallel' 3D integration that stacks several 2D wavers on top of each other using relatively huge and few vertical connections between the tiers, 'sequential 3D integration' builds the CMOS tiers on a single substrate using photolitography. This way, the density of vertical connections is of the same order of magnitude as the horizontal connections in 2D. So transistors of a circuit module can be placed freely in any tier with no significant disadvantages. This offers new opportunities to make tiers with different types of transistors and thus to make circuits that include different types of transistors, e.g transistors that are optimized for the digital signal domain in one and transistors that are optimized for the analog signal domain in another. So mixed signal circuits can be designed with highly optimized components, as illustrated by this conceptual recursive SAR ADC:
Optimized devices are not the only advantage though. In general, due to 3D placement the total interconnect wiring will be reduced enhancing speed and power efficiency. Furthermore, the LETI 3D sequential integration process allows to have a ground plane between the tiers, insulating the analog from the digital domain for reduced cross-talk noise. So there are a bunch of new possibilities to optimize circuits and circuit layout here that we want to start to explore.
In particular we shall be looking at sensor front ends for Langmuir probes that measure ion density in plasma and that are used on sounding rockets that are launched into the ionosphere within the 4DSpace strategic research initiative at UiO.